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Scheduler for multiprocessor system switch with selective pairing

Patent ·
OSTI ID:1167015
System, method and computer program product for scheduling threads in a multiprocessing system with selective pairing of processor cores for increased processing reliability. A selective pairing facility is provided that selectively connects, i.e., pairs, multiple microprocessor or processor cores to provide one highly reliable thread (or thread group). The method configures the selective pairing facility to use checking provide one highly reliable thread for high-reliability and allocate threads to corresponding processor cores indicating need for hardware checking. The method configures the selective pairing facility to provide multiple independent cores and allocate threads to corresponding processor cores indicating inherent resilience.
Research Organization:
International Business Machines Corporation, Armonk, NY (United States)
Sponsoring Organization:
USDOE
Assignee:
International Business Machines Corporation (Armonk, NY)
Patent Number(s):
8,930,752
Application Number:
13/027,960
OSTI ID:
1167015
Country of Publication:
United States
Language:
English

References (4)

Transactional memory: architectural support for lock-free data structures conference January 1993
A Genetic Algorithm for Reliability-Oriented Task Assignment With$widetildek$Duplications in Distributed Systems journal March 2006
The Stanford Hydra CMP journal January 2000
Transactional Memory Coherence and Consistency journal March 2004

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