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Title: Use of a hard mask for formation of gate and dielectric via nanofilament field emission devices

Patent ·
OSTI ID:873578

A process for fabricating a nanofilament field emission device in which a via in a dielectric layer is self-aligned to gate metal via structure located on top of the dielectric layer. By the use of a hard mask layer located on top of the gate metal layer, inert to the etch chemistry for the gate metal layer, and in which a via is formed by the pattern from etched nuclear tracks in a trackable material, a via is formed by the hard mask will eliminate any erosion of the gate metal layer during the dielectric via etch. Also, the hard mask layer will protect the gate metal layer while the gate structure is etched back from the edge of the dielectric via, if such is desired. This method provides more tolerance for the electroplating of a nanofilament in the dielectric via and sharpening of the nanofilament.

Research Organization:
Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
DOE Contract Number:
W-7405-ENG-48
Assignee:
Regents of University of California (Oakland, CA)
Patent Number(s):
US 6193870
OSTI ID:
873578
Country of Publication:
United States
Language:
English

References (3)

Low-voltage field emission from tungsten fiber arrays in a stabilized zirconia matrix journal June 1987
Vacuum microelectronics-1992 journal June 1992
The art and science and other aspects of making sharp tips journal March 1991