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Title: Address-based filtering for load/store speculation

Patent ·
OSTI ID:1998359

Address-based filtering for load/store speculation includes maintaining a filtering table including table entries associated with ranges of addresses; in response to receiving an ordering check triggering transaction, querying the filtering table using a target address of the ordering check triggering transaction to determine if an instruction dependent upon the ordering check triggering transaction has previously been generated a physical address; and in response to determining that the filtering table lacks an indication that the instruction dependent upon the ordering check triggering transaction has previously been generated a physical address, bypassing a lookup operation in an ordering violation memory structure to determine whether the instruction dependent upon the ordering check triggering transaction is currently in-flight.

Research Organization:
Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States); Advanced Micro Devices, Inc., Santa Clara, CA (United States)
Sponsoring Organization:
USDOE
DOE Contract Number:
AC52-07NA27344; B620717
Assignee:
Advanced Micro Devices, Inc. (Santa Clara, CA)
Patent Number(s):
11,645,073
Application Number:
17/238,844
OSTI ID:
1998359
Resource Relation:
Patent File Date: 04/23/2021
Country of Publication:
United States
Language:
English

References (17)

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Value prediction in a processor for providing speculative execution patent-application October 2004
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Decomposing the load-store queue by function for power reduction and scalability journal March 2006
Memory ordering: a value-based approach journal November 2004
A Two-Level Load/Store Queue Based on Execution Locality conference June 2008
Methods and apparatus for controlling speculative execution of instructions based on a multiaccess memory condition patent-application February 2003
Fine-Grain Power Breakdown of Modern Out-of-Order Cores and Its Implications on Skylake-Based Systems journal December 2016
Method and apparatus for reordering memory operations in a superscalar or very long instruction word processor patent April 1997
Load/store dependency predictor optimization for replayed loads patent October 2019
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The Superfluous Load Queue conference October 2018
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