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Filtering micro-operations for a micro-operation cache in a processor

Patent ·
OSTI ID:2222120
; ; ;
A processor includes a micro-operation cache having a plurality of micro-operation cache entries for storing micro-operations decoded from instruction groups and a micro-operation filter having a plurality of micro-operation filter table entries for storing identifiers of instruction groups for which the micro-operations are predicted dead on fill if stored in the micro-operation cache. The micro-operation filter receives an identifier for an instruction group. The micro-operation filter then prevents a copy of the micro-operations from the first instruction group from being stored in the micro-operation cache when a micro-operation filter table entry includes an identifier that matches the first identifier.
Research Organization:
Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States); Advanced Micro Devices, Inc., Santa Clara, CA (United States)
Sponsoring Organization:
USDOE
DOE Contract Number:
AC52-07NA27344
Assignee:
Advanced Micro Devices, Inc. (Santa Clara, CA)
Patent Number(s):
11,726,783
Application Number:
16/856,832
OSTI ID:
2222120
Country of Publication:
United States
Language:
English

References (4)

Sampling Dead Block Prediction for Last-Level Caches conference December 2010
Dead-block prediction & dead-block correlating prefetchers conference January 2001
Micro-operation cache
  • Solomon, Baruch; Mendelson, Avi; Orenstein, Doron
  • Proceedings of the 2001 international symposium on Low power electronics and design - ISLPED '01 https://doi.org/10.1145/383082.383085
conference January 2001
Multiperspective reuse prediction conference October 2017

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