Implementing a micro-operation cache with compaction

Patent · Tue May 25 04:00:00 EDT 2021

OSTI ID:1823995

Kotra, Jagadish B.; Kalamatianos, John

Systems, apparatuses, and methods for compacting multiple groups of micro-operations into individual cache lines of a micro-operation cache are disclosed. A processor includes at least a decode unit and a micro-operation cache. When a new group of micro-operations is decoded and ready to be written to the micro-operation cache, the micro-operation cache determines which set is targeted by the new group of micro-operations. If there is a way in this set that can store the new group without evicting any existing group already stored in the way, then the new group is stored into the way with the existing group(s) of micro-operations. Metadata is then updated to indicate that the new group of micro-operations has been written to the way. Additionally, the micro-operation cache manages eviction and replacement policy at the granularity of micro-operation groups rather than at the granularity of cache lines.

• Research Organization: Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
• Sponsoring Organization: USDOE
• DOE Contract Number: AC52-07NA27344
• Assignee: Advanced Micro Devices, Inc. (Santa Clara, CA)
• Patent Number(s): 11,016,763
• Application Number: 16/297,358
• OSTI ID: 1823995
• Country of Publication: United States
• Language: English