Bit error protection in cache memories

Patent · Tue Feb 02 00:00:00 EST 2021

OSTI ID:1805470

Kalamatianos, John; Ganapathy, Shrikanth

A computing device having a cache memory that is configured in a write-back mode is described. A cache controller in the cache memory acquires, from a record of bit errors that are present in each of a plurality of portions of the cache memory, a number of bit errors in a portion of the cache memory. The cache controller detects a coherency state of data stored in the portion of the cache memory. Based on the coherency state and the number of bit errors, the cache controller selects an error protection from among a plurality of error protections. The cache controller uses the selected error protection to protect the data stored in the portion of the cache memory from errors.

• Research Organization: Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
• Sponsoring Organization: USDOE
• DOE Contract Number: AC52-07NA27344; B620717
• Assignee: Advanced Micro Devices, Inc. (Santa Clara, CA)
• Patent Number(s): 10,908,991
• Application Number: 16/123,489
• OSTI ID: 1805470
• Resource Relation: Patent File Date: 09/06/2018
• Country of Publication: United States
• Language: English