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Title: Architecture for on-die interconnect

Patent ·
OSTI ID:1457407
; ; ;

In an embodiment, an apparatus includes: a plurality of islands configured on a semiconductor die, each of the plurality of islands having a plurality of cores; and a plurality of network switches configured on the semiconductor die and each associated with one of the plurality of islands, where each network switch includes a plurality of output ports, a first set of the output ports are each to couple to the associated network switch of an island via a point-to-point interconnect and a second set of the output ports are each to couple to the associated network switches of a plurality of islands via a point-to-multipoint interconnect. Other embodiments are described and claimed.

Research Organization:
Intel Corporation, Santa Clara, CA (United States)
Sponsoring Organization:
USDOE
DOE Contract Number:
B600738
Assignee:
Intel Corporation (Santa Clara, CA)
Patent Number(s):
9,998,401
Application Number:
15/042,402
OSTI ID:
1457407
Resource Relation:
Patent File Date: 2016 Feb 12
Country of Publication:
United States
Language:
English

References (14)

Multi-chip package and interposer with signal line compression patent October 2015
Interconnect to Communicate Information Uni-Directionally patent-application June 2014
Scaleable low-latency switch for usage in an interconnect structure patent September 2001
Cost-Efficient Dragonfly Topology for Large-Scale Systems conference January 2009
Network device configured to generate empty route for limiting number of withdrawal messages patent August 2016
Methods and semiconductor devices with wiring layer fill structures to improve planarization uniformity patent February 2004
Method and Device for Scheduling Unicast and Multicast Traffic in an Interconnecting Fabric patent-application September 2008
Integration of Processor and Input/Output Hub patent-application December 2011
Die-Stacked Device With Partitioned Multi-Hop Network patent-application June 2014
Inter-Processor Communication Channel Including Power-Down Functionality patent-application April 2010
Semiconductor device patent April 2014
Cost-Efficient Dragonfly Topology for Large-Scale Systems journal January 2009
Data structure-less distributed fabric multicast patent October 2014
Express Cube Topologies for on-Chip Interconnects conference February 2009

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