skip to main content
OSTI.GOV title logo U.S. Department of Energy
Office of Scientific and Technical Information

Title: Architecture for on-die interconnect

Abstract

In an embodiment, an apparatus includes: a plurality of islands configured on a semiconductor die, each of the plurality of islands having a plurality of cores; and a plurality of network switches configured on the semiconductor die and each associated with one of the plurality of islands, where each network switch includes a plurality of output ports, a first set of the output ports are each to couple to the associated network switch of an island via a point-to-point interconnect and a second set of the output ports are each to couple to the associated network switches of a plurality of islands via a point-to-multipoint interconnect. Other embodiments are described and claimed.

Inventors:
; ; ;
Publication Date:
Research Org.:
Intel Corporation, Santa Clara, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1243036
Patent Number(s):
9,287,208
Application Number:
14/524,622
Assignee:
Intel Corporation (Santa Clara, CA) OSTI
DOE Contract Number:  
B600738
Resource Type:
Patent
Resource Relation:
Patent File Date: 2014 Oct 27
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Citation Formats

Khare, Surhud, More, Ankit, Somasekhar, Dinesh, and Dunning, David S. Architecture for on-die interconnect. United States: N. p., 2016. Web.
Khare, Surhud, More, Ankit, Somasekhar, Dinesh, & Dunning, David S. Architecture for on-die interconnect. United States.
Khare, Surhud, More, Ankit, Somasekhar, Dinesh, and Dunning, David S. Tue . "Architecture for on-die interconnect". United States. https://www.osti.gov/servlets/purl/1243036.
@article{osti_1243036,
title = {Architecture for on-die interconnect},
author = {Khare, Surhud and More, Ankit and Somasekhar, Dinesh and Dunning, David S.},
abstractNote = {In an embodiment, an apparatus includes: a plurality of islands configured on a semiconductor die, each of the plurality of islands having a plurality of cores; and a plurality of network switches configured on the semiconductor die and each associated with one of the plurality of islands, where each network switch includes a plurality of output ports, a first set of the output ports are each to couple to the associated network switch of an island via a point-to-point interconnect and a second set of the output ports are each to couple to the associated network switches of a plurality of islands via a point-to-multipoint interconnect. Other embodiments are described and claimed.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Mar 15 00:00:00 EDT 2016},
month = {Tue Mar 15 00:00:00 EDT 2016}
}

Patent:

Save / Share: