Apparatus and method for fusion of compute and switching functions of exascale system into a single component by using configurable network-on-chip fabric with distributed dual mode input-output ports and programmable network interfaces

Khare, Surhud; Somasekhar, Dinesh; More, Ankit; Dunning, David S.; Borkar, Nitin Y.; Borkar, Shekhar Y.

Title: Apparatus and method for fusion of compute and switching functions of exascale system into a single component by using configurable network-on-chip fabric with distributed dual mode input-output ports and programmable network interfaces

Patent · Tue Jun 05 00:00:00 EDT 2018

OSTI ID:1455200

Khare, Surhud; Somasekhar, Dinesh; More, Ankit; Dunning, David S.; Borkar, Nitin Y.; Borkar, Shekhar Y.

Described is an apparatus which comprises: a Network-On-Chip fabric using crossbar switches, having distributed ingress and egress ports; and a dual-mode network interface coupled to at least one crossbar switch, the dual-mode network interface is to include: a dual-mode circuitry; a controller operable to: configure the dual-mode circuitry to transmit and receive differential signals via the egress and ingress ports, respectively, and configure the dual-mode circuitry to transmit and receive signal-ended signals via the egress and ingress ports, respectively.

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Research Organization:: Intel Corporation, Santa Clara, CA (United States)

Sponsoring Organization:: USDOE

DOE Contract Number:: B608115

Assignee:: Intel Corporation (Santa Clara, CA)

Patent Number(s):: 9,992,135

Application Number:: 14/967,166

OSTI ID:: 1455200

Resource Relation:: Patent File Date: 2015 Dec 11

Country of Publication:: United States

Language:: English

References (9)

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Mesh network Olofsson, Andreas D. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8531943 US Patent Document 8,531,943	patent	September 2013
Processing system with interspersed processors DMA-FIFO Dobbs, Carl S.; Trocino, Michael R.; Bindloss, Keith M. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/9424213 US Patent Document 9,424,213	patent	August 2016
Multiprocessor Node Controller Circuit and Method Deneroff, Martin M.; Kaldani, Givargis G.; Koren, Yuval https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20090024833 US Patent Document 12/181202; 20090024833	patent-application	January 2009
Systems and Methods for Dynamic Routing in a Multiprocessor Network Using Local Congestion Sensing Abts, Dennis Charles; Klausler, Peter Michael; Marty, Michael https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20120170582 US Patent Document 12/985013; 20120170582	patent-application	July 2012
Modular Decoupled Crossbar for On-Chip Router Park, Dongkonk; Vaidya, Aniruddha; Kumar, Akhilesh https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20140376557 US Patent Document 13/994801; 20140376557	patent-application	December 2014
Architecture and Method for Hybrid Circuit-Switched and Packet-Switched Router Anders, Mark A.; Chen, Gregory K.; Kaul, Himanshu https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20150071282 US Patent Document 14/129544; 20150071282	patent-application	March 2015
Directional Two-Dimensional Router and Interconnection Network for Field Programmable Gate Arrays, and Other Circuits and Applications of the Router and Network Gray, Jan Stephen https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20160344629 US Patent Document 14/986532; 20160344629	patent-application	November 2016

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