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Title: Structured wafer for device processing

Patent ·
OSTI ID:1132054
;

A structured wafer that includes through passages is used for device processing. Each of the through passages extends from or along one surface of the structured wafer and forms a pattern on a top surface area of the structured wafer. The top surface of the structured wafer is bonded to a device layer via a release layer. Devices are processed on the device layer, and are released from the structured wafer using etchant. The through passages within the structured wafer allow the etchant to access the release layer to thereby remove the release layer.

Research Organization:
Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
Sponsoring Organization:
USDOE
DOE Contract Number:
AC04-94AL85000
Assignee:
Sandia Corporation (Albuquerque, NM)
Patent Number(s):
8,729,673
Application Number:
13/239,181
OSTI ID:
1132054
Resource Relation:
Patent File Date: 2011 Sep 21
Country of Publication:
United States
Language:
English

References (4)

Die singulation using deep silicon etching patent August 2004
Die singulation method and package formed thereby patent August 2012
Method for chip singulation patent-application March 2006
Method for Transferring an Epitaxial Layer from a Donor Wafer to a System Wafer Appertaining to Microsystems Technology patent-application December 2010

Cited By (2)

Supporting member separation method patent April 2017
Fast process flow, on-wafer interconnection and singulation for MEPV patent January 2017

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