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Title: Scheduler for multiprocessor system switch with selective pairing

System, method and computer program product for scheduling threads in a multiprocessing system with selective pairing of processor cores for increased processing reliability. A selective pairing facility is provided that selectively connects, i.e., pairs, multiple microprocessor or processor cores to provide one highly reliable thread (or thread group). The method configures the selective pairing facility to use checking provide one highly reliable thread for high-reliability and allocate threads to corresponding processor cores indicating need for hardware checking. The method configures the selective pairing facility to provide multiple independent cores and allocate threads to corresponding processor cores indicating inherent resilience.
Authors:
; ;
Publication Date:
OSTI Identifier:
1167015
Report Number(s):
8,930,752
13/027,960
DOE Contract Number:
B554331
Resource Type:
Patent
Resource Relation:
Patent File Date: 2011 Feb 15
Research Org:
International Business Machines Corporation, Armonk, NY (United States)
Sponsoring Org:
USDOE
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING