Substrate structures for InP-based devices
Abstract
A substrate structure for an InP-based semiconductor device having an InP based film is disclosed. The substrate structure includes a substrate region having a lightweight bulk substrate and an upper GaAs layer. An interconnecting region is disposed between the substrate region and the InP-based device. The interconnecting region includes a compositionally graded intermediate layer substantially lattice-matched at one end to the GaAs layer and substantially lattice-matched at the opposite end to the InP-based film. The interconnecting region further includes a dislocation mechanism disposed between the GaAs layer and the InP-based film in cooperation with the graded intermediate layer, the buffer mechanism blocking and inhibiting propagation of threading dislocations between the substrate region, and the InP-based device.
- Inventors:
-
- Golden, CO
- Lakewood, CO
- Issue Date:
- Research Org.:
- Midwest Research Institute, Kansas City, MO (United States)
- OSTI Identifier:
- 867566
- Patent Number(s):
- 4963949
- Assignee:
- United States of America as represented of United States (Washington, DC)
- Patent Classifications (CPCs):
-
H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES
Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC Y10S - TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- DOE Contract Number:
- AC02-83CH10093
- Resource Type:
- Patent
- Country of Publication:
- United States
- Language:
- English
- Subject:
- substrate; structures; inp-based; devices; structure; semiconductor; device; inp; based; film; disclosed; region; lightweight; bulk; upper; gaas; layer; interconnecting; disposed; compositionally; graded; intermediate; substantially; lattice-matched; opposite; dislocation; mechanism; cooperation; buffer; blocking; inhibiting; propagation; threading; dislocations; compositionally graded; semiconductor device; intermediate layer; gaas layer; substrate region; mechanism disposed; substrate structure; interconnecting region; /257/136/438/
Citation Formats
Wanlass, Mark W, and Sheldon, Peter. Substrate structures for InP-based devices. United States: N. p., 1990.
Web.
Wanlass, Mark W, & Sheldon, Peter. Substrate structures for InP-based devices. United States.
Wanlass, Mark W, and Sheldon, Peter. Mon .
"Substrate structures for InP-based devices". United States. https://www.osti.gov/servlets/purl/867566.
@article{osti_867566,
title = {Substrate structures for InP-based devices},
author = {Wanlass, Mark W and Sheldon, Peter},
abstractNote = {A substrate structure for an InP-based semiconductor device having an InP based film is disclosed. The substrate structure includes a substrate region having a lightweight bulk substrate and an upper GaAs layer. An interconnecting region is disposed between the substrate region and the InP-based device. The interconnecting region includes a compositionally graded intermediate layer substantially lattice-matched at one end to the GaAs layer and substantially lattice-matched at the opposite end to the InP-based film. The interconnecting region further includes a dislocation mechanism disposed between the GaAs layer and the InP-based film in cooperation with the graded intermediate layer, the buffer mechanism blocking and inhibiting propagation of threading dislocations between the substrate region, and the InP-based device.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Mon Jan 01 00:00:00 EST 1990},
month = {Mon Jan 01 00:00:00 EST 1990}
}