Level-conversion circuits utilizing level-dependent inverter supply voltages
Abstract
Voltage level conversion circuits include PMOS pull-down devices or NMOS pull-up devices, and inverters with outputs that determine gate voltages of these devices. The inverters are powered by moving supply voltages, for example complementary supply voltages generated from a pair of cross-coupled inverters. The cross-coupled inverters may implement a data storage latch with the moving supply voltages generated from the internal data storage nodes of the latch.
- Inventors:
- Issue Date:
- Research Org.:
- Nvidia Corp., Santa Clara, CA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 2293901
- Patent Number(s):
- 11824533
- Application Number:
- 17/814,752
- Assignee:
- NVIDIA Corporation (Santa Clara, CA)
- DOE Contract Number:
- B609487
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 07/25/2022
- Country of Publication:
- United States
- Language:
- English
Citation Formats
Turner, Walker Joseph, Poulton, John, and Song, Sanquan. Level-conversion circuits utilizing level-dependent inverter supply voltages. United States: N. p., 2023.
Web.
Turner, Walker Joseph, Poulton, John, & Song, Sanquan. Level-conversion circuits utilizing level-dependent inverter supply voltages. United States.
Turner, Walker Joseph, Poulton, John, and Song, Sanquan. Tue .
"Level-conversion circuits utilizing level-dependent inverter supply voltages". United States. https://www.osti.gov/servlets/purl/2293901.
@article{osti_2293901,
title = {Level-conversion circuits utilizing level-dependent inverter supply voltages},
author = {Turner, Walker Joseph and Poulton, John and Song, Sanquan},
abstractNote = {Voltage level conversion circuits include PMOS pull-down devices or NMOS pull-up devices, and inverters with outputs that determine gate voltages of these devices. The inverters are powered by moving supply voltages, for example complementary supply voltages generated from a pair of cross-coupled inverters. The cross-coupled inverters may implement a data storage latch with the moving supply voltages generated from the internal data storage nodes of the latch.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Nov 21 00:00:00 EST 2023},
month = {Tue Nov 21 00:00:00 EST 2023}
}
Works referenced in this record:
8.6 A 6.5-to-23.3fJ/b/mm balanced charge-recycling bus in 16nm FinFET CMOS at 1.7-to-2.6Gb/s/wire with clock forwarding and low-crosstalk contraflow wiring
conference, January 2016
- Wilson, John M.; Fojtik, Matthew R.; Poulton, John W.
- 2016 IEEE International Solid-State Circuits Conference (ISSCC)
Ultra low power LVDS driver with built in impedance termination to supply and ground rails
patent, June 2010
- Khoury, Elie; Sessions, Dc
- US Patent Document 7,746,121