Elevated voltage level I.sub.DDQ failure testing of integrated circuits
Abstract
Burn in testing of static CMOS IC's is eliminated by I.sub.DDQ testing at elevated voltage levels. These voltage levels are at least 25% higher than the normal operating voltage for the IC but are below voltage levels that would cause damage to the chip.
- Inventors:
-
- Albuquerque, NM
- Issue Date:
- Research Org.:
- Sandia National Laboratories (SNL), Albuquerque, NM, and Livermore, CA (United States)
- OSTI Identifier:
- 870427
- Patent Number(s):
- 5519333
- Assignee:
- Sandia Corporation (Albuquerque, NM)
- Patent Classifications (CPCs):
-
G - PHYSICS G01 - MEASURING G01R - MEASURING ELECTRIC VARIABLES
- DOE Contract Number:
- AC04-94AL85000
- Resource Type:
- Patent
- Country of Publication:
- United States
- Language:
- English
- Subject:
- elevated; voltage; level; ddq; failure; testing; integrated; circuits; burn; static; cmos; eliminated; levels; 25; normal; operating; below; damage; chip; voltage levels; operating voltage; integrated circuits; integrated circuit; normal operating; voltage level; elevated voltage; /324/
Citation Formats
Righter, Alan W. Elevated voltage level I.sub.DDQ failure testing of integrated circuits. United States: N. p., 1996.
Web.
Righter, Alan W. Elevated voltage level I.sub.DDQ failure testing of integrated circuits. United States.
Righter, Alan W. Mon .
"Elevated voltage level I.sub.DDQ failure testing of integrated circuits". United States. https://www.osti.gov/servlets/purl/870427.
@article{osti_870427,
title = {Elevated voltage level I.sub.DDQ failure testing of integrated circuits},
author = {Righter, Alan W},
abstractNote = {Burn in testing of static CMOS IC's is eliminated by I.sub.DDQ testing at elevated voltage levels. These voltage levels are at least 25% higher than the normal operating voltage for the IC but are below voltage levels that would cause damage to the chip.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {1996},
month = {1}
}
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