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Title: Bufferless communication for redundant multithreading using register permutation

Abstract

Systems, apparatuses, and methods for implementing bufferless communication for redundant multithreading applications using register permutation are disclosed. In one embodiment, a system includes a parallel processing unit, a register file, and a scheduler. The scheduler is configured to cause execution of a plurality of threads to be performed in lockstep on the parallel processing unit. The plurality of threads include a first thread and a second thread executing on adjacent first and second lanes, respectively, of the parallel processing unit. The second thread is configured to perform a register permute operation from a first register location to a second register location in a first instruction cycle, with the second register location associated with the second processing lane. The second thread is configured to read from the second register location in a second instruction cycle, wherein the first and second instruction cycles are successive instruction cycles.

Inventors:
;
Issue Date:
Research Org.:
Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1568400
Patent Number(s):
10303472
Application Number:
15/359,236
Assignee:
Advanced Micro Devices, Inc. (Santa Clara, CA)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
DOE Contract Number:  
AC52-07NA27344; B609201
Resource Type:
Patent
Resource Relation:
Patent File Date: 11/22/2016
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Citation Formats

Lowell, Daniel I., and Gupta, Manish. Bufferless communication for redundant multithreading using register permutation. United States: N. p., 2019. Web.
Lowell, Daniel I., & Gupta, Manish. Bufferless communication for redundant multithreading using register permutation. United States.
Lowell, Daniel I., and Gupta, Manish. Tue . "Bufferless communication for redundant multithreading using register permutation". United States. https://www.osti.gov/servlets/purl/1568400.
@article{osti_1568400,
title = {Bufferless communication for redundant multithreading using register permutation},
author = {Lowell, Daniel I. and Gupta, Manish},
abstractNote = {Systems, apparatuses, and methods for implementing bufferless communication for redundant multithreading applications using register permutation are disclosed. In one embodiment, a system includes a parallel processing unit, a register file, and a scheduler. The scheduler is configured to cause execution of a plurality of threads to be performed in lockstep on the parallel processing unit. The plurality of threads include a first thread and a second thread executing on adjacent first and second lanes, respectively, of the parallel processing unit. The second thread is configured to perform a register permute operation from a first register location to a second register location in a first instruction cycle, with the second register location associated with the second processing lane. The second thread is configured to read from the second register location in a second instruction cycle, wherein the first and second instruction cycles are successive instruction cycles.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2019},
month = {5}
}

Patent:

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