Determining diagnostic coverage for memory using redundant execution

Bramley, Richard Gavin; Shirvani, Philip Payman; Saxena, Nirmal Raj

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Title: Determining diagnostic coverage for memory using redundant execution

Abstract

Memory, used by a computer to store data, is generally prone to faults, including permanent faults (i.e. relating to a lifetime of the memory hardware), and also transient faults (i.e. relating to some external cause) which are otherwise known as soft errors. Since soft errors can change the state of the data in the memory and thus cause errors in applications reading and processing the data, there is a desire to characterize the degree of vulnerability of the memory to soft errors. In particular, once the vulnerability for a particular memory to soft errors has been characterized, cost/reliability trade-offs can be determined, or soft error detection mechanisms (e.g. parity) may be selectively employed for the memory. In some cases, memory faults can be diagnosed by redundant execution and a diagnostic coverage may be determined.

Inventors:: Bramley, Richard Gavin; Shirvani, Philip Payman; Saxena, Nirmal Raj

Issue Date:: Tue Nov 30 00:00:00 EST 2021

Research Org.:: NVIDIA Corporation, Santa Clara, CA (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1860124

Patent Number(s):: 11188442

Application Number:: 16/849,697

Assignee:: NVIDIA Corporation (Santa Clara, CA)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F11/073 - {in a memory management context, e.g. virtual memory or cache management
G06F11/0757 - {by exceeding a time limit, i.e. time-out, e.g. watchdogs}
G06F11/1068 - {in sector programmable memories, e.g. flash disk
G06F11/3419 - {by assessing time}
G06F11/3457 - {Performance evaluation by simulation}
G06F11/3471 - {Address tracing}
G06F11/3476 - {Data logging
G06F2201/81 - Threshold
G06F2201/88 - Monitoring involving counting

Show less

DOE Contract Number:: B620719

Resource Type:: Patent

Resource Relation:: Patent File Date: 04/15/2020

Country of Publication:: United States

Language:: English

Citation Formats


                    Bramley, Richard Gavin, Shirvani, Philip Payman, and Saxena, Nirmal Raj. Determining diagnostic coverage for memory using redundant execution.  United States: N. p., 2021. 
        Web.

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                    Bramley, Richard Gavin, Shirvani, Philip Payman, & Saxena, Nirmal Raj. Determining diagnostic coverage for memory using redundant execution.  United States.

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                    Bramley, Richard Gavin, Shirvani, Philip Payman, and Saxena, Nirmal Raj. Tue .  
        "Determining diagnostic coverage for memory using redundant execution".  United States.  https://www.osti.gov/servlets/purl/1860124.

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@article{osti_1860124,

  title        = {Determining diagnostic coverage for memory using redundant execution},

  author       = {Bramley, Richard Gavin and Shirvani, Philip Payman and Saxena, Nirmal Raj},

  abstractNote = {Memory, used by a computer to store data, is generally prone to faults, including permanent faults (i.e. relating to a lifetime of the memory hardware), and also transient faults (i.e. relating to some external cause) which are otherwise known as soft errors. Since soft errors can change the state of the data in the memory and thus cause errors in applications reading and processing the data, there is a desire to characterize the degree of vulnerability of the memory to soft errors. In particular, once the vulnerability for a particular memory to soft errors has been characterized, cost/reliability trade-offs can be determined, or soft error detection mechanisms (e.g. parity) may be selectively employed for the memory. In some cases, memory faults can be diagnosed by redundant execution and a diagnostic coverage may be determined.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {Tue Nov 30 00:00:00 EST 2021},

  month        = {Tue Nov 30 00:00:00 EST 2021}

}

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Similar Records

Title: Determining diagnostic coverage for memory using redundant execution

Abstract

Citation Formats

Method and Apparatus for Injecting Errors into Memory patent-application, October 2013

System and method for correcting soft errors in random access memory devices patent-application, October 2002

Data Storage Device and Method of Managing a Cache in a Data Storage Device patent-application, August 2013

Improvements in Backward Analysis for Determining Fault Masking Factors patent-application, March 2013

Method and apparatus for memory vulnerability prediction patent, June 2020

Systems and methods for efficient memory access patent, July 2015

Register Liveness Analysis for SIMD Architectures patent-application, October 2012

Methodology for fixing Qcrit at design timing impact patent, October 2005

Lightweight checkpoint technique for resilience against soft errors patent, May 2021

Single event upset error detection within an integrated circuit patent-application, July 2007

Software initialization of USB devices on a single bus patent, April 2014

Parity protection of a register patent, May 2017

Systems and methods for programming configurable logic devices via USB patent, May 2015

Hardware execution driven application level derating calculation for soft error rate analysis patent, February 2015

System and method of recovering from soft memory errors patent, November 2005

Soft error detection patent, November 2014

Detecting and mitigating soft errors using duplicative instructions patent, February 2008

Memory Apparatus and Methods Thereof for Preventing Read Errors on Weak Pages in a Non-Volatile Memory System patent-application, October 2014

System performance simulator patent, April 2013

Common interface for handling exception interface name with additional prefix and suffix for handling exceptions in environment services patterns patent, August 2002

Dynamic Cache Write Policy patent-application, July 2014

Determining Soft Error Infliction Probability patent-application, August 2015

Vulnerability estimation for cache memory patent, July 2015

Determination and correction of physical circuit event related errors of a hardware design patent, July 2019

Vulnerability Estimation for Cache Memory patent-application, September 2014

Metal oxide semiconductor (MOS) device comprising a buried region under drain patent, April 2011

Register transfer level simulation using a graphics processor patent, November 2010

Object Liveness Tracking for Use in a Processing Device Cache patent-application, October 2014

Methods and circuitry for identifying logic regions affected by soft errors patent, March 2017

Simulation Apparatus and Simulation Method patent-application, May 2013

Method and Apparatus for Injecting Errors into Memory
patent-application, October 2013

System and method for correcting soft errors in random access memory devices
patent-application, October 2002

Data Storage Device and Method of Managing a Cache in a Data Storage Device
patent-application, August 2013

Improvements in Backward Analysis for Determining Fault Masking Factors
patent-application, March 2013

Method and apparatus for memory vulnerability prediction
patent, June 2020

Systems and methods for efficient memory access
patent, July 2015

Register Liveness Analysis for SIMD Architectures
patent-application, October 2012

Methodology for fixing Qcrit at design timing impact
patent, October 2005

Lightweight checkpoint technique for resilience against soft errors
patent, May 2021

Single event upset error detection within an integrated circuit
patent-application, July 2007

Software initialization of USB devices on a single bus
patent, April 2014

Parity protection of a register
patent, May 2017

Systems and methods for programming configurable logic devices via USB
patent, May 2015

Hardware execution driven application level derating calculation for soft error rate analysis
patent, February 2015

System and method of recovering from soft memory errors
patent, November 2005

Soft error detection
patent, November 2014

Detecting and mitigating soft errors using duplicative instructions
patent, February 2008

Memory Apparatus and Methods Thereof for Preventing Read Errors on Weak Pages in a Non-Volatile Memory System
patent-application, October 2014

System performance simulator
patent, April 2013

Common interface for handling exception interface name with additional prefix and suffix for handling exceptions in environment services patterns
patent, August 2002

Dynamic Cache Write Policy
patent-application, July 2014

Determining Soft Error Infliction Probability
patent-application, August 2015

Vulnerability estimation for cache memory
patent, July 2015

Determination and correction of physical circuit event related errors of a hardware design
patent, July 2019

Vulnerability Estimation for Cache Memory
patent-application, September 2014

Metal oxide semiconductor (MOS) device comprising a buried region under drain
patent, April 2011

Register transfer level simulation using a graphics processor
patent, November 2010

Object Liveness Tracking for Use in a Processing Device Cache
patent-application, October 2014

Methods and circuitry for identifying logic regions affected by soft errors
patent, March 2017

Simulation Apparatus and Simulation Method
patent-application, May 2013