Ultra-low power processor-in-memory architecture
Abstract
An apparatus including a memory array comprising a plurality of rows and a plurality of columns. A switch electrically connects to a particular row of the plurality of rows of the memory array per cycle. An energy storage unit is electrically connected to the memory array through the switch, wherein the energy storage unit is electrically connected in a series with an effective capacitance between ground and the particular row of the plurality of rows of the memory array to which the switch is connected to recycle energy from the memory array.
- Inventors:
- Issue Date:
- Research Org.:
- Sandia National Laboratories (SNL), Albuquerque, NM, and Livermore, CA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1482180
- Patent Number(s):
- 10083080
- Application Number:
- 15/824,879
- Assignee:
- National Technology & Engineering Solutions of Sandia, LLC (Albuquerque, NM)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
- DOE Contract Number:
- AC04-94AL85000; NA0003525
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 2017 Nov 28
- Country of Publication:
- United States
- Language:
- English
Citation Formats
DeBenedictis, Erik. Ultra-low power processor-in-memory architecture. United States: N. p., 2018.
Web.
DeBenedictis, Erik. Ultra-low power processor-in-memory architecture. United States.
DeBenedictis, Erik. Tue .
"Ultra-low power processor-in-memory architecture". United States. https://www.osti.gov/servlets/purl/1482180.
@article{osti_1482180,
title = {Ultra-low power processor-in-memory architecture},
author = {DeBenedictis, Erik},
abstractNote = {An apparatus including a memory array comprising a plurality of rows and a plurality of columns. A switch electrically connects to a particular row of the plurality of rows of the memory array per cycle. An energy storage unit is electrically connected to the memory array through the switch, wherein the energy storage unit is electrically connected in a series with an effective capacitance between ground and the particular row of the plurality of rows of the memory array to which the switch is connected to recycle energy from the memory array.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Sep 25 00:00:00 EDT 2018},
month = {Tue Sep 25 00:00:00 EDT 2018}
}
Save to My Library
You must Sign In or Create an Account in order to save documents to your library.
Works referenced in this record:
Semiconductor memory with power-on reset controlled latched row line repeaters
patent, June 1996
- Slemmer, William C.; McClure, David C.
- US Patent Document 5,526,318
Energy-Efficient Row Driver for Programming Phase Change Memory
patent-application, June 2013
- Lam, Chung H.
- US Patent Application 13/335155; 20130163320
A low-power sense amplifier for adiabatic memory using memristor
conference, December 2012
- Urata, Yuki; Takahashi, Yasuhiro; Sekine, Toshikazu
1.1 TMACS/mW Fine-Grained Stochastic Resonant Charge-Recycling Array Processor
journal, April 2012
- Karakiewicz, Rafal; Genov, Roman; Cauwenberghs, Gert
- IEEE Sensors Journal, Vol. 12, Issue 4, p. 785-792
Computation Hardware with High-Bandwidth Memory Interface
patent-application, March 2015
- Strauss, Karin; Fowers, Jeremy
- US Patent Document 14/015872; 20150067273
Improvement of Electronic-Computer Reliability through the Use of Redundancy
journal, September 1961
- Brown, W. G.; Tierney, J.; Wasserman, R.
- IEEE Transactions on Electronic Computers, Vol. EC-10, Issue 3, p. 407-416
Low power signal processing architectures using residue arithmetic
conference, January 1998
- Bhardwaj, M.; Balaram, A.
Compression system and method for accelerating sparse matrix computations
patent, July 2014
- Lumsdaine, Andrew; Willcock, Jeremiah J.
- US Patent Document 8,775,495
Self-checked computation using residue arithmetic
journal, January 1966
- Watson, R. W.; Hastings, C. W.
- Proceedings of the IEEE, Vol. 54, Issue 12, p. 1920-1931
Dynamic Scaling Of Graphics Processor Execution Resources
patent-application, February 2016
- Kaburlasos, Nikos; Samson, Eric
- US Patent Application 14/463573; 20160054782
Energy-Efficient Digital Signal Processing via Voltage-Overscaling-Based Residue Number System
journal, July 2013
- Chen, Jienan; Hu, Jianhao
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 21, Issue 7, p. 1322-1332
Design of a Repairable Redundant Computer
journal, October 1962
- Teoste, Rein
- IEEE Transactions on Electronic Computers, Vol. EC-11, Issue 5, p. 643-649
Switching power supply for lowered distribution system disturbance
patent, February 2001
- Parker, Francis J.; Maitin, Steven R.
- US Patent Document 6,194,881
Micro-Electric-Mechanical Module
patent-application, November 2007
- Yazdi, Navid
- US Patent Application 11/671130; 20070273463
A three-port adiabatic register file suitable for embedded applications
conference, January 1998
- Avery, Stephan; Jabri, Marwan
Sustaining moore's law in embedded computing through probabilistic and approximate design: retrospects and prospects
conference, January 2009
- Palem, Krishna V.; Chakrapani, Lakshmi N.B.; Kedem, Zvi M.
Iterative stage as dividend operand prescaler for fixed-radix division
patent, March 2014
- Old, Gordon I.
- US Patent Document 8,667,044
Apparatus and method for allocating shared storage areas to parallel processors for multiplication of sparse matrix and vector
patent, August 2016
- Usui, Tetsuzou
- US Patent Document 9,418,048
Mapping irregular applications to DIVA, a PIM-based data-intensive architecture
conference, January 1999
- Hall, Mary; Srivastava, Apoorv; Athas, William