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Title: Ultra-low power processor-in-memory architecture

An apparatus including a memory array comprising a plurality of rows and a plurality of columns. A switch electrically connects to a particular row of the plurality of rows of the memory array per cycle. An energy storage unit is electrically connected to the memory array through the switch, wherein the energy storage unit is electrically connected in a series with an effective capacitance between ground and the particular row of the plurality of rows of the memory array to which the switch is connected to recycle energy from the memory array.
Inventors:
Issue Date:
OSTI Identifier:
1482180
Assignee:
National Technology & Engineering Solutions of Sandia, LLC (Albuquerque, NM) SNL
Patent Number(s):
10,083,080
Application Number:
15/824,879
Contract Number:
AC04-94AL85000; NA0003525
Resource Relation:
Patent File Date: 2017 Nov 28
Research Org:
Sandia National Laboratories (SNL), Albuquerque, NM, and Livermore, CA (United States)
Sponsoring Org:
USDOE
Country of Publication:
United States
Language:
English

Works referenced in this record:

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