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Title: Ultra-low power processor-in-memory architecture

Abstract

An apparatus including a memory array comprising a plurality of rows and a plurality of columns. A switch electrically connects to a particular row of the plurality of rows of the memory array per cycle. An energy storage unit is electrically connected to the memory array through the switch, wherein the energy storage unit is electrically connected in a series with an effective capacitance between ground and the particular row of the plurality of rows of the memory array to which the switch is connected to recycle energy from the memory array.

Inventors:
Issue Date:
Research Org.:
Sandia National Laboratories (SNL), Albuquerque, NM, and Livermore, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1482180
Patent Number(s):
10083080
Application Number:
15/824,879
Assignee:
National Technology & Engineering Solutions of Sandia, LLC (Albuquerque, NM)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
DOE Contract Number:  
AC04-94AL85000; NA0003525
Resource Type:
Patent
Resource Relation:
Patent File Date: 2017 Nov 28
Country of Publication:
United States
Language:
English

Citation Formats

DeBenedictis, Erik. Ultra-low power processor-in-memory architecture. United States: N. p., 2018. Web.
DeBenedictis, Erik. Ultra-low power processor-in-memory architecture. United States.
DeBenedictis, Erik. Tue . "Ultra-low power processor-in-memory architecture". United States. https://www.osti.gov/servlets/purl/1482180.
@article{osti_1482180,
title = {Ultra-low power processor-in-memory architecture},
author = {DeBenedictis, Erik},
abstractNote = {An apparatus including a memory array comprising a plurality of rows and a plurality of columns. A switch electrically connects to a particular row of the plurality of rows of the memory array per cycle. An energy storage unit is electrically connected to the memory array through the switch, wherein the energy storage unit is electrically connected in a series with an effective capacitance between ground and the particular row of the plurality of rows of the memory array to which the switch is connected to recycle energy from the memory array.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2018},
month = {9}
}

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Works referenced in this record:

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