Global to push GA events into
skip to main content

Title: Processor-in-memory-and-storage architecture

A method and apparatus for performing reliable general-purpose computing. Each sub-core of a plurality of sub-cores of a processor core processes a same instruction at a same time. A code analyzer receives a plurality of residues that represents a code word corresponding to the same instruction and an indication of whether the code word is a memory address code or a data code from the plurality of sub-cores. The code analyzer determines whether the plurality of residues are consistent or inconsistent. The code analyzer and the plurality of sub-cores perform a set of operations based on whether the code word is a memory address code or a data code and a determination of whether the plurality of residues are consistent or inconsistent.
Issue Date:
OSTI Identifier:
National Technology & Engineering Solutions of Sandia, LLC (Albuquerque, NM) SNL-A
Patent Number(s):
Application Number:
Contract Number:
Resource Relation:
Patent File Date: 2015 Aug 20
Research Org:
Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
Sponsoring Org:
Country of Publication:
United States

Works referenced in this record:

A three-port adiabatic register file suitable for embedded applications
conference, January 1998

Improvement of Electronic-Computer Reliability through the Use of Redundancy
journal, September 1961
  • Brown, W. G.; Tierney, J.; Wasserman, R.
  • IEEE Transactions on Electronic Computers, Vol. EC-10, Issue 3, p. 407-416
  • DOI: 10.1109/TEC.1961.5219229

Mapping irregular applications to DIVA, a PIM-based data-intensive architecture
conference, January 1999

Energy-Efficient Digital Signal Processing via Voltage-Overscaling-Based Residue Number System
journal, July 2013
  • Chen, Jienan; Hu, Jianhao
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 21, Issue 7, p. 1322-1332
  • DOI: 10.1109/TVLSI.2012.2205953

1.1 TMACS/mW Fine-Grained Stochastic Resonant Charge-Recycling Array Processor
journal, April 2012
  • Karakiewicz, Rafal; Genov, Roman; Cauwenberghs, Gert
  • IEEE Sensors Journal, Vol. 12, Issue 4, p. 785-792
  • DOI: 10.1109/JSEN.2011.2113393

Sustaining moore's law in embedded computing through probabilistic and approximate design: retrospects and prospects
conference, January 2009

In Quest of the “Next Switch”: Prospects for Greatly Reduced Power Dissipation in a Successor to the Silicon Field-Effect Transistor
journal, December 2010

A low-power sense amplifier for adiabatic memory using memristor
conference, December 2012

Self-checked computation using residue arithmetic
journal, January 1966
  • Watson, R. W.; Hastings, C. W.
  • Proceedings of the IEEE, Vol. 54, Issue 12, p. 1920-1931
  • DOI: 10.1109/PROC.1966.5275