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Title: Processor-in-memory-and-storage architecture

A method and apparatus for performing reliable general-purpose computing. Each sub-core of a plurality of sub-cores of a processor core processes a same instruction at a same time. A code analyzer receives a plurality of residues that represents a code word corresponding to the same instruction and an indication of whether the code word is a memory address code or a data code from the plurality of sub-cores. The code analyzer determines whether the plurality of residues are consistent or inconsistent. The code analyzer and the plurality of sub-cores perform a set of operations based on whether the code word is a memory address code or a data code and a determination of whether the plurality of residues are consistent or inconsistent.
Inventors:
Issue Date:
OSTI Identifier:
1415442
Assignee:
National Technology & Engineering Solutions of Sandia, LLC (Albuquerque, NM) SNL-A
Patent Number(s):
9,858,144
Application Number:
14/831,711
Contract Number:
AC04-94AL85000
Resource Relation:
Patent File Date: 2015 Aug 20
Research Org:
Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
Sponsoring Org:
USDOE
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Other works cited in this record:

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