Computational processor-in-memory with enhanced strided memory access
Abstract
A computational memory for a computer. The memory includes a memory bank having a selected-row buffer and being configured to store records up to a number, K. The memory also includes an accumulator connected to the memory bank, the accumulator configured to store up to K records. The memory also includes an arithmetic and logic unit (ALU) connected to the accumulator and to the selected row buffer of the memory bank, the ALU having an indirect network of 2K ports for reading and writing records in the memory bank and the accumulator, and the ALU further physically configured to operate as a sorting network. The memory also includes a controller connected to the memory bank, the ALU, and the accumulator, the controller being hardware configured to direct operation of the ALU.
- Inventors:
- Issue Date:
- Research Org.:
- Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
- Sponsoring Org.:
- USDOE National Nuclear Security Administration (NNSA)
- OSTI Identifier:
- 1805584
- Patent Number(s):
- 10936230
- Application Number:
- 15/881,502
- Assignee:
- National Technology & Engineering Solutions of Sandia, LLC (Albuquerque, NM)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
- DOE Contract Number:
- NA0003525
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 01/26/2018
- Country of Publication:
- United States
- Language:
- English
Citation Formats
DeBenedictis, Erik. Computational processor-in-memory with enhanced strided memory access. United States: N. p., 2021.
Web.
DeBenedictis, Erik. Computational processor-in-memory with enhanced strided memory access. United States.
DeBenedictis, Erik. Tue .
"Computational processor-in-memory with enhanced strided memory access". United States. https://www.osti.gov/servlets/purl/1805584.
@article{osti_1805584,
title = {Computational processor-in-memory with enhanced strided memory access},
author = {DeBenedictis, Erik},
abstractNote = {A computational memory for a computer. The memory includes a memory bank having a selected-row buffer and being configured to store records up to a number, K. The memory also includes an accumulator connected to the memory bank, the accumulator configured to store up to K records. The memory also includes an arithmetic and logic unit (ALU) connected to the accumulator and to the selected row buffer of the memory bank, the ALU having an indirect network of 2K ports for reading and writing records in the memory bank and the accumulator, and the ALU further physically configured to operate as a sorting network. The memory also includes a controller connected to the memory bank, the ALU, and the accumulator, the controller being hardware configured to direct operation of the ALU.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Mar 02 00:00:00 EST 2021},
month = {Tue Mar 02 00:00:00 EST 2021}
}
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