Scalable polylithic on-package integratable apparatus and method
Abstract
Described is an apparatus which comprises: a first die including: a processing core; a crossbar switch coupled to the processing core; and a first edge interface coupled to the crossbar switch; and a second die including: a first edge interface positioned at a periphery of the second die and coupled to the first edge interface of the first die, wherein the first edge interface of the first die and the first edge interface of the second die are positioned across each other; a clock synchronization circuit coupled to the second edge interface; and a memory interface coupled to the clock synchronization circuit.
- Inventors:
- Issue Date:
- Research Org.:
- Intel Corporation, Santa Clara, CA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1411393
- Patent Number(s):
- 9837391
- Application Number:
- 14/967,231
- Assignee:
- Intel Corporation (Santa Clara, CA)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES
- DOE Contract Number:
- B608115
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 2015 Dec 11
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 42 ENGINEERING; 97 MATHEMATICS AND COMPUTING
Citation Formats
Khare, Surhud, Somasekhar, Dinesh, and Borkar, Shekhar Y. Scalable polylithic on-package integratable apparatus and method. United States: N. p., 2017.
Web.
Khare, Surhud, Somasekhar, Dinesh, & Borkar, Shekhar Y. Scalable polylithic on-package integratable apparatus and method. United States.
Khare, Surhud, Somasekhar, Dinesh, and Borkar, Shekhar Y. Tue .
"Scalable polylithic on-package integratable apparatus and method". United States. https://www.osti.gov/servlets/purl/1411393.
@article{osti_1411393,
title = {Scalable polylithic on-package integratable apparatus and method},
author = {Khare, Surhud and Somasekhar, Dinesh and Borkar, Shekhar Y.},
abstractNote = {Described is an apparatus which comprises: a first die including: a processing core; a crossbar switch coupled to the processing core; and a first edge interface coupled to the crossbar switch; and a second die including: a first edge interface positioned at a periphery of the second die and coupled to the first edge interface of the first die, wherein the first edge interface of the first die and the first edge interface of the second die are positioned across each other; a clock synchronization circuit coupled to the second edge interface; and a memory interface coupled to the clock synchronization circuit.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Dec 05 00:00:00 EST 2017},
month = {Tue Dec 05 00:00:00 EST 2017}
}
Works referenced in this record:
Memory controller with multi-protocol interface
patent, January 2013
- Bresniker, Kirk
- US Patent Document 8,347,005
Layered Crossbar For Interconnection Of Multiple Processors And Shared Memories
patent-application, September 2007
- Purcell, Stephen; Cheng, Christopher
- US Patent Application 11/463842; 20070208901
Forming Multiprocessor Systems Using Dual Processors
patent-application, July 2012
- Sistla, Krishnakanth; Srinivasa, Ganapati
- US Patent Application 13/422806; 20120179878
Final Faulty Core Recovery Mechanisms For A Two-Dimensional Network On A Processor Array
patent-application, April 2014
- Alvarez-Icaza Rivera, Rodrigo; Arthur, John; Barth, John
- US Patent Application 13/631496; 20140095923
Die-Stacked Device With Partitioned Multi-Hop Network
patent-application, June 2014
- Thottethodi, Mithuna; Loh, Gabriel
- US Patent Application 13/726142; 20140177626
On-Package Multiprocessor Ground-Referenced Single-Ended Interconnect
patent-application, September 2014
- Dally, William; Khailany, Brucek; Poulton, John
- US Patent Application 13/946980; 20140266416
Edge-Aware Synchronization Of A Data Signal
patent-application, June 2016
- Chen, Gregory; Anders, Mark; Kaul, Himanshu
- US Patent Application 14/567987; 20160173074