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Title: Device-packaging method and apparatus for optoelectronic circuits

An optoelectronic device package and a method for its fabrication are provided. The device package includes a lid die and an active die that is sealed or sealable to the lid die and in which one or more optical waveguides are integrally defined. The active die includes one or more active device regions, i.e. integral optoelectronic devices or etched cavities for placement of discrete optoelectronic devices. Optical waveguides terminate at active device regions so that they can be coupled to them. Slots are defined in peripheral parts of the active dies. At least some of the slots are aligned with the ends of integral optical waveguides so that optical fibers or optoelectronic devices inserted in the slots can optically couple to the waveguides.
Inventors:
; ;
Issue Date:
OSTI Identifier:
1353067
Assignee:
Sandia Corporation SNL-A
Patent Number(s):
9,632,261
Application Number:
14/819,293
Contract Number:
AC04-94AL85000
Resource Relation:
Patent File Date: 2015 Aug 05
Research Org:
Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
Sponsoring Org:
USDOE
Country of Publication:
United States
Language:
English
Subject:
36 MATERIALS SCIENCE; 71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSICS

Other works cited in this record:

Lid wafer bond packaging and micromachining
patent, June 1999

Optical device module
patent, December 2002

Opto-electronic transceiver module and hermetically sealed housing therefore
patent, January 2003

Opto-electronic substrates with electrical and optical interconnections and methods for making
patent, August 2003

System and method for the fabrication of an electro-optical module
patent, February 2010

Optical connectors and a method of production thereof
patent, November 2014

Layer separation optimization in CMOS compatible multilayer optical networks
conference, May 2013
  • Jones, Adam M.; DeRose, Christopher T.; Lentine, Anthony L.
  • 2013 Optical Interconnects Conference
  • DOI: 10.1109/OIC.2013.6552924

Wafer-Level Packaging Technology for 10 Gbps TOSAs
conference, May 2005
  • Sherrer, D.W.; Brese, N.; Fisher, J.
  • Proceedings Electronic Components and Technology, 2005. ECTC '05
  • DOI: 10.1109/ECTC.2005.1441440

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