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Title: Repairable chip bonding/interconnect process

Abstract

A repairable, chip-to-board interconnect process which addresses cost and testability issues in the multi-chip modules. This process can be carried out using a chip-on-sacrificial-substrate technique, involving laser processing. This process avoids the curing/solvent evolution problems encountered in prior approaches, as well is resolving prior plating problems and the requirements for fillets. For repairable high speed chip-to-board connection, transmission lines can be formed on the sides of the chip from chip bond pads, ending in a gull wing at the bottom of the chip for subsequent solder.

Inventors:
 [1];  [2];  [2];  [3]
  1. Berkeley, CA
  2. Livermore, CA
  3. Tracy, CA
Publication Date:
Research Org.:
Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)
OSTI Identifier:
871076
Patent Number(s):
US 5653019
Assignee:
Regents of University of California (Oakland, CA)
DOE Contract Number:  
W-7405-ENG-48
Resource Type:
Patent
Country of Publication:
United States
Language:
English
Subject:
repairable; chip; bonding; interconnect; process; chip-to-board; addresses; cost; testability; issues; multi-chip; modules; carried; chip-on-sacrificial-substrate; technique; involving; laser; processing; avoids; curing; solvent; evolution; encountered; prior; approaches; resolving; plating; requirements; fillets; speed; connection; transmission; lines; formed; bond; pads; gull; bottom; subsequent; solder; multi-chip modules; transmission lines; transmission line; bond pads; laser processing; multi-chip module; chip bond; interconnect process; /29/257/438/

Citation Formats

Bernhardt, Anthony F, Contolini, Robert J, Malba, Vincent, and Riddle, Robert A. Repairable chip bonding/interconnect process. United States: N. p., 1997. Web.
Bernhardt, Anthony F, Contolini, Robert J, Malba, Vincent, & Riddle, Robert A. Repairable chip bonding/interconnect process. United States.
Bernhardt, Anthony F, Contolini, Robert J, Malba, Vincent, and Riddle, Robert A. Wed . "Repairable chip bonding/interconnect process". United States. https://www.osti.gov/servlets/purl/871076.
@article{osti_871076,
title = {Repairable chip bonding/interconnect process},
author = {Bernhardt, Anthony F and Contolini, Robert J and Malba, Vincent and Riddle, Robert A},
abstractNote = {A repairable, chip-to-board interconnect process which addresses cost and testability issues in the multi-chip modules. This process can be carried out using a chip-on-sacrificial-substrate technique, involving laser processing. This process avoids the curing/solvent evolution problems encountered in prior approaches, as well is resolving prior plating problems and the requirements for fillets. For repairable high speed chip-to-board connection, transmission lines can be formed on the sides of the chip from chip bond pads, ending in a gull wing at the bottom of the chip for subsequent solder.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {1997},
month = {1}
}

Patent:

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