Repairable chip bonding/interconnect process
Patent
·
OSTI ID:871076
- Berkeley, CA
- Livermore, CA
- Tracy, CA
A repairable, chip-to-board interconnect process which addresses cost and testability issues in the multi-chip modules. This process can be carried out using a chip-on-sacrificial-substrate technique, involving laser processing. This process avoids the curing/solvent evolution problems encountered in prior approaches, as well is resolving prior plating problems and the requirements for fillets. For repairable high speed chip-to-board connection, transmission lines can be formed on the sides of the chip from chip bond pads, ending in a gull wing at the bottom of the chip for subsequent solder.
- Research Organization:
- Lawrence Livermore National Laboratory (LLNL), Livermore, CA
- DOE Contract Number:
- W-7405-ENG-48
- Assignee:
- Regents of University of California (Oakland, CA)
- Patent Number(s):
- US 5653019
- OSTI ID:
- 871076
- Country of Publication:
- United States
- Language:
- English
Similar Records
Repairable chip bonding/interconnect process
Laser tabbed die: A repairable, high-speed die-interconnection technology. 1994 LDRD final report 93-SR-089
Solder bump height dependence of Josephson chip-to-card interconnection inductance using flip-chip bonding technique
Patent
·
Tue Aug 05 00:00:00 EDT 1997
·
OSTI ID:516937
Laser tabbed die: A repairable, high-speed die-interconnection technology. 1994 LDRD final report 93-SR-089
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·
Fri Sep 01 00:00:00 EDT 1995
·
OSTI ID:120877
Solder bump height dependence of Josephson chip-to-card interconnection inductance using flip-chip bonding technique
Journal Article
·
Thu Sep 01 00:00:00 EDT 1983
· J. Appl. Phys.; (United States)
·
OSTI ID:5727556
Related Subjects
/29/257/438/
addresses
approaches
avoids
bond
bond pads
bonding
bottom
carried
chip
chip bond
chip-on-sacrificial-substrate
chip-to-board
connection
cost
curing
encountered
evolution
fillets
formed
gull
interconnect
interconnect process
involving
issues
laser
laser processing
lines
modules
multi-chip
multi-chip module
multi-chip modules
pads
plating
prior
process
processing
repairable
requirements
resolving
solder
solvent
speed
subsequent
technique
testability
transmission
transmission line
transmission lines
addresses
approaches
avoids
bond
bond pads
bonding
bottom
carried
chip
chip bond
chip-on-sacrificial-substrate
chip-to-board
connection
cost
curing
encountered
evolution
fillets
formed
gull
interconnect
interconnect process
involving
issues
laser
laser processing
lines
modules
multi-chip
multi-chip module
multi-chip modules
pads
plating
prior
process
processing
repairable
requirements
resolving
solder
solvent
speed
subsequent
technique
testability
transmission
transmission line
transmission lines