Repairable chip bonding/interconnect process
Patent
·
OSTI ID:516937
A repairable, chip-to-board interconnect process which addresses cost and testability issues in the multi-chip modules is disclosed. This process can be carried out using a chip-on-sacrificial-substrate technique, involving laser processing. This process avoids the curing/solvent evolution problems encountered in prior approaches, as well is resolving prior plating problems and the requirements for fillets. For repairable high speed chip-to-board connection, transmission lines can be formed on the sides of the chip from chip bond pads, ending in a gull wing at the bottom of the chip for subsequent solder. 10 figs.
- Research Organization:
- University of California
- Sponsoring Organization:
- USDOE, Washington, DC (United States)
- DOE Contract Number:
- W-7405-ENG-48
- Assignee:
- Univ. of California, Oakland, CA (United States)
- Patent Number(s):
- US 5,653,019/A/
- Application Number:
- PAN: 8-522,471
- OSTI ID:
- 516937
- Country of Publication:
- United States
- Language:
- English
Similar Records
Repairable chip bonding/interconnect process
Laser tabbed die: A repairable, high-speed die-interconnection technology. 1994 LDRD final report 93-SR-089
Solder bump height dependence of Josephson chip-to-card interconnection inductance using flip-chip bonding technique
Patent
·
Tue Dec 31 23:00:00 EST 1996
·
OSTI ID:871076
Laser tabbed die: A repairable, high-speed die-interconnection technology. 1994 LDRD final report 93-SR-089
Technical Report
·
Fri Sep 01 00:00:00 EDT 1995
·
OSTI ID:120877
Solder bump height dependence of Josephson chip-to-card interconnection inductance using flip-chip bonding technique
Journal Article
·
Thu Sep 01 00:00:00 EDT 1983
· J. Appl. Phys.; (United States)
·
OSTI ID:5727556