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Title: Static ferroelectric memory transistor having improved data retention

Patent ·
OSTI ID:870703
 [1];  [2]
  1. 7716 Wm. Moyers Ave., NE., Albuquerque, NM 87112
  2. 12808 Lillian Pl., NE., Albuquerque, NM 87112

An improved ferroelectric FET structure in which the ferroelectric layer is doped to reduce retention loss. A ferroelectric FET according to the present invention includes a semiconductor layer having first and second contacts thereon, the first and second contacts being separated from one another. The ferroelectric FET also includes a bottom electrode and a ferroelectric layer which is sandwiched between the semiconductor layer and the bottom electrode. The ferroelectric layer is constructed from a perovskite structure of the chemical composition ABO.sub.3 wherein the B site comprises first and second elements and a dopant element that has an oxidation state greater than +4 in sufficient concentration to impede shifts in the resistance measured between the first and second contacts with time. The ferroelectric FET structure preferably comprises Pb in the A-site. The first and second elements are preferably Zr and Ti, respectively. The preferred B-site dopants are Niobium, Tantalum, and Tungsten at concentrations between 1% and 8%.

Research Organization:
Sandia National Laboratories (SNL), Albuquerque, NM, and Livermore, CA (United States)
DOE Contract Number:
AC04-76
Assignee:
Evans, Jr., Joseph T. (13609 Verbena Pl., N.E., Albuquerque, NM 87112);Warren, William L. (7716 Wm. Moyers Ave., NE., Albuquerque, NM 87112);Tuttle, Bruce A. (12808 Lillian Pl., NE., Albuquerque, NM 87112)
Patent Number(s):
US 5578846
OSTI ID:
870703
Country of Publication:
United States
Language:
English