Elevated voltage level I.sub.DDQ failure testing of integrated circuits
                            Patent
                            ·
                            
                            
                            
                    
                                
                                OSTI ID:870427
                                
                            
                        - Albuquerque, NM
Burn in testing of static CMOS IC's is eliminated by I.sub.DDQ testing at elevated voltage levels. These voltage levels are at least 25% higher than the normal operating voltage for the IC but are below voltage levels that would cause damage to the chip.
- Research Organization:
- SANDIA CORP
- DOE Contract Number:
- AC04-94AL85000
- Assignee:
- Sandia Corporation (Albuquerque, NM)
- Patent Number(s):
- US 5519333
- OSTI ID:
- 870427
- Country of Publication:
- United States
- Language:
- English
Similar Records
                                
                                
                                    
                                        
                                        Elevated voltage level I{sub DDQ} failure testing of integrated circuits
                                        
Integrated circuit failure analysis by low-energy charge-induced voltage alteration
Integrated circuit failure analysis by low-energy charge-induced voltage alteration
                        
                                            Patent
                                            ·
                                            Tue May 21 00:00:00 EDT 1996
                                            
                                            ·
                                            OSTI ID:238071
                                        
                                        
                                        
                                    
                                
                                    
                                        Integrated circuit failure analysis by low-energy charge-induced voltage alteration
                                            Patent
                                            ·
                                            Sun Dec 31 23:00:00 EST 1995
                                            
                                            ·
                                            OSTI ID:870444
                                        
                                        
                                        
                                    
                                
                                    
                                        Integrated circuit failure analysis by low-energy charge-induced voltage alteration
                                            Patent
                                            ·
                                            Tue Jun 04 00:00:00 EDT 1996
                                            
                                            ·
                                            OSTI ID:242594