Method for reducing or eliminating interface defects in mismatched semiconductor eiplayers
- Ithaca, NY
The present invention and process relates to crystal lattice mismatched semiconductor composite having a first semiconductor layer and a second semiconductor growth layer deposited thereon to form an interface wherein the growth layer can be deposited at thicknesses in excess of the critical thickness, even up to about 10x critical thickness. Such composite has an interface which is substantially free of interface defects. For example, the size of the growth areas in a mismatched In.sub.0.05 Ga.sub.0.95 As/(001)GaAs interface was controlled by fabricating 2-.mu.m high pillars of various lateral geometries and lateral dimensions before the epitaxial deposition of 3500.ANG. of In.sub.0.05 Ga.sub.0.95 As. The linear dislocation density at the interface was reduced from >5000 dislocations/cm to about zero for 25-.mu.m lateral dimensions and to less than 800 dislocations/cm for lateral dimensions as large as 100 .mu.m. The fabricated pillars control the lateral dimensions of the growth layer and block the glide of misfit dislocations with the resultant decrease in dislocation density.
- Research Organization:
- Cornell University
- DOE Contract Number:
- FG02-86ER45278
- Assignee:
- Cornell Research Foundation, Inc. (Ithaca, NY)
- Patent Number(s):
- US 5032893
- OSTI ID:
- 867916
- Country of Publication:
- United States
- Language:
- English
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Related Subjects
001
05
100
10x
2-
25-
3500
5000
800
95
ang
block
cm
composite
control
controlled
critical
crystal
crystal lattice
decrease
defects
density
deposited
deposited thereon
deposition
dimensions
dislocation
dislocation density
dislocations
eiplayers
eliminating
eliminating interface
epitaxial
epitaxial deposition
example
excess
fabricated
fabricating
form
free
gaas
geometries
glide
growth
interface
interface defects
lateral
lateral dimensions
lattice
lattice mismatch
lattice mismatched
layer
layer deposited
linear
method
misfit
mismatched
mismatched semiconductor
pillars
process
process relates
reduced
reducing
relates
resultant
semiconductor
semiconductor composite
semiconductor growth
semiconductor layer
size
substantially
substantially free
thereon
thickness
thicknesses
various
zero