Method of making high breakdown voltage semiconductor device
Patent
·
OSTI ID:867396
- Scotia, NY
- Jonesville, NY
A semiconductor device having at least one P-N junction and a multiple-zone junction termination extension (JTE) region which uniformly merges with the reverse blocking junction is disclosed. The blocking junction is graded into multiple zones of lower concentration dopant adjacent termination to facilitate merging of the JTE to the blocking junction and placing of the JTE at or near the high field point of the blocking junction. Preferably, the JTE region substantially overlaps the graded blocking junction region. A novel device fabrication method is also provided which eliminates the prior art step of separately diffusing the JTE region.
- Assignee:
- General Electric Company (Schenectady, NY)
- Patent Number(s):
- US 4927772
- OSTI ID:
- 867396
- Country of Publication:
- United States
- Language:
- English
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