Method of making high breakdown voltage semiconductor device

Patent · Tue May 22 04:00:00 EDT 1990

OSTI ID:5571324

Arthur, S D; Temple, V A.K.

This patent describes improvement in the process of fabricating a semiconductor device including, when complete, at least one P-N junction, a first region of semiconductor material of one conductivity type having an upper surface and forming one side of the junction, a second region of semiconductor material having a lower surface and forming the other side of the junction, the second region being formed within the first region with conductivity type opposite that of the first region; and wherein the P-N junction includes a terminated portion at the upper surface of the first region, the second region includes a graded region adjacent to termination of the P-N junction, and the first region at a width W{sub D} when the junction is reverse-biased to its ideal breakdown voltage; the improvement comprises: forming a first mask of not so uniform thickness on the semiconductor device adjacent to the terminated portion to be used in forming a junction termination extension region; simultaneously doping the first and second portions of the first region through the first mask with the same concentration of dopant to form in the first region, a first zone contiguous with the terminated portion and a second zone adjacent the first zone; forming a second mask of not so uniform thickness on the semiconductor device adjacent the terminated portion and remote from the balance of the junction termination extension region, to be used in forming the second region including the graded region; simultaneously doping the first and second portions of the first region through the second mask with the same concentration of dopant to form in the first region the second region such that the second region has a first zone contiguous with the terminated portion and a second zone adjacent the first zone; and simultaneously diffusing the junction termination extension implant and the second region dopant implant.

• Assignee: General Electric Co., Schenectady, NY (United States)
• Patent Number(s): A; US 4927772
• Application Number: PPN: US 7-358057
• OSTI ID: 5571324
• Country of Publication: United States
• Language: English

Related Subjects

42 ENGINEERING
426000* -- Engineering-- Components
Electron Devices & Circuits-- (1990-)
DESIGN
FABRICATION
JUNCTIONS
MATERIALS
P-N JUNCTIONS
SEMICONDUCTOR DEVICES
SEMICONDUCTOR JUNCTIONS
SEMICONDUCTOR MATERIALS