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U.S. Department of Energy
Office of Scientific and Technical Information

Planarization of metal films for multilevel interconnects

Patent ·
OSTI ID:866887

In the fabrication of multilevel integrated circuits, each metal layer is anarized by heating to momentarily melt the layer. The layer is melted by sweeping laser pulses of suitable width, typically about 1 microsecond duration, over the layer in small increments. The planarization of each metal layer eliminates irregular and discontinuous conditions between successive layers. The planarization method is particularly applicable to circuits having ground or power planes and allows for multilevel interconnects. Dielectric layers can also be planarized to produce a fully planar multilevel interconnect structure. The method is useful for the fabrication of VLSI circuits, particularly for wafer-scale integration.

Research Organization:
Lawrence Livermore National Laboratory (LLNL), Livermore, CA
DOE Contract Number:
W-7405-ENG-48
Assignee:
United States of America as represented by Department of Energy (Washington, DC)
Patent Number(s):
US 4814578
OSTI ID:
866887
Country of Publication:
United States
Language:
English