Planarization of metal films for multilevel interconnects

Patent · Mon Jun 24 00:00:00 EDT 1985

OSTI ID:5656740

Tuckerman, D B

In the fabrication of multilevel integrated circuits, each metal layer is planarized by heating to momentarily melt the layer. The layer is melted by sweeping lase pulses of suitable width, typically about 1 microsecond duration, over the layer in small increments. The planarization of each metal layer eliminates irregular and discontinuous conditions between successive layers. The planarization method is particularly applicable to circuits having ground or power planes and allows for multilevel interconnects. Dielectric layers can also be planarized to produce a fully planar multilevel interconnect structure. The method is useful for the fabrication of VLSI circuits, particularly for wafer-scale integration.

• Research Organization: Lawrence Livermore National Lab., CA (USA)
• DOE Contract Number: W-7405-ENG-48
• Assignee: Dept. of Energy
• Patent Number(s): None
• Application Number: ON: DE86013743
• OSTI ID: 5656740
• Country of Publication: United States
• Language: English

Related Subjects

42 ENGINEERING
420800* -- Engineering-- Electronic Circuits & Devices-- (-1989)
ELECTRONIC CIRCUITS
FABRICATION
INTEGRATED CIRCUITS
JOINING
LASER WELDING
MICROELECTRONIC CIRCUITS
WELDING