Planarization of metal films for multilevel interconnects

Patent · Fri Aug 23 00:00:00 EDT 1985

OSTI ID:5534461

Tuckerman, D B

In the fabrication of multilevel integrated circuits, each metal layer is planarized by heating to momentarily melt the layer. The layer is melted by sweeping laser pulses of suitable width, typically about 1 microsecond duration, over the layer in small increments. The planarization of each metal layer eliminates irregular and discontinuous conditions between successive layers. The planarization method is particularly applicable to circuits having ground or power planes and allows for multilevel interconnects. Dielectric layers can also be planarized to produce a fully planar multilevel interconnect structure. The method is useful for the fabrication of VLSI circuits, particularly for wafer-scale integration.

• Research Organization: Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
• DOE Contract Number: W-7405-ENG-48
• Assignee: Dept. of Energy
• Application Number: ON: DE86013747
• OSTI ID: 5534461
• Resource Relation: Other Information: Portions of this document are illegible in microfiche products
• Country of Publication: United States
• Language: English

Related Subjects

36 MATERIALS SCIENCE
ALUMINIUM
MATERIALS WORKING
INTEGRATED CIRCUITS
FABRICATION
SILICON ALLOYS
LASERS
SILICON
USES
ALLOYS
ELECTRONIC CIRCUITS
ELEMENTS
METALS
MICROELECTRONIC CIRCUITS
SEMIMETALS
360601* - Other Materials- Preparation & Manufacture
360101 - Metals & Alloys- Preparation & Fabrication