Planarization of metal films for multilevel interconnects

Patent · Tue Mar 21 00:00:00 EST 1989

OSTI ID:7266783

Tuckerman, D B

In the fabrication of multilevel integrated circuits, each metal layer is planarized by heating to momentarily melt the layer. The layer is melted by sweeping laser pulses of suitable width, typically about 1 microsecond duration, over the layer in small increments. The planarization of each metal layer eliminates irregular and discontinuous conditions between successive layers. The planarization method is particularly applicable to circuits having ground or power planes and allows for multilevel interconnects. Dielectric layers can also be planarized to produce a fully planar multilevel interconnect structure. The method is useful for the fabrication of VLSI circuits, particularly for wafer-scale integration. 6 figs.

• DOE Contract Number: W-7405-ENG-48
• Assignee: Dept. of Energy, Washington, DC (United States)
• Patent Number(s): US 4814578; A
• Application Number: PPN: US 7-065473
• OSTI ID: 7266783
• Resource Relation: Patent File Date: 23 Jun 1987
• Country of Publication: United States
• Language: English

Related Subjects

42 ENGINEERING
INTEGRATED CIRCUITS
FABRICATION
METALS
SURFACE FINISHING
LASER RADIATION
MELTING
ROUGHNESS
ELECTROMAGNETIC RADIATION
ELECTRONIC CIRCUITS
ELEMENTS
MICROELECTRONIC CIRCUITS
PHASE TRANSFORMATIONS
RADIATIONS
SURFACE PROPERTIES
426000* - Engineering- Components
Electron Devices & Circuits- (1990-)