Semiconductor Manufacturing Modeling Final Report CRADA No. TC-1069-94
- LLNL
The Semiconductor Industry Association (SIA) roadmap projection for 1 GHz on-chip clock speeds and 64 Gbits/Chip DRAM technology by the year 2005 requires scaling the minimum feature size of CMOS devices down to 100nm. This requirement has profound implications for device processing.. As physical constraints begin to limit device integration and characteristics, existing processing techniques must increasingly be understood quantitatively and modeled with unprecedented precision. Such advances will necessitate a fundamental improvement in our basic understanding of microstructure evolution during processing, and this can only be obtained through the development and validation of advanced physically-based predictive materials modeling computational tools. The work in this CRADA addressed these concerns directly, and the resuhs will therefore greatly benefit the US semiconductor manufacturing and defense industries by aiding in the reduction of the time-to-market cycle, and by making it possible to substitute. many high cost empirical design steps in manufacturing with much lower cost Technology Computer Aided Design (TCAD) processes. Four research areas are described, Bulk Processing, Interconnects, Etch, and Fundamental Atomic Models. The technical program, based on an extensive project work plan developed by SRC, LLNL, SNL, and LANL, included extensive use of Local Density Approximation, Tight Binding Methods, and combined Molecular Dynamics and Monte Carlo methods (KINETIC Monte Carlo) to cover length and time scales necessary to adequately model processes in the manufacturing of LSIC. The work was also of great benefit to DOE and LLNL. The improvements in capability are of generic value, deriving their specific value in actual applications. For example, the techniques developed in this CRADA for B/Si interactions, thin film growth, etch processing are all of interest to the electronics industry but are equally applicable to the improvement and understanding of aging of Pu which is of great interest to DOE. The effort has initiated new avenues of development at LLNL. While the problem of automatically generating tight-binding force representations has not been solved in this work the new techniques developed here will greatly facilitate understanding of the �transferability� problem which has so far held up the achievement of this goal.
- Research Organization:
- Lawrence Livermore National Laboratory (LLNL), Livermore, CA
- Sponsoring Organization:
- USDOE Office of Defense Programs (DP)
- DOE Contract Number:
- W-7405-ENG-48
- OSTI ID:
- 757015
- Report Number(s):
- UCRL-ID-138157; LLNL-TR-747341; CRADA No. TC-1069-94
- Country of Publication:
- United States
- Language:
- English
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