Emmy/Unibus interface design specification. Technical note No. 109

Technical Report · Sat Jan 01 04:00:00 EST 1977

OSTI ID:7318689

Shih, M

The interface, named ''MATCH'' (a bus translation unit), is designed to allow communication between the Emmy system bus and a DEC PDP-11 Unibus. The translation unit consists of five functionally independent modules: an Emmy I/0 interface unit, an address translation unit, two-ported data path, a microprogramed translation sequencer, and a Unibus I/0 interface unit. The Emmy I/0 interface unit allows the Emmy system to act as bus master on the Unibus. The 32-bit Emmy bus address is truncated to 18 bits for use on the Unibus. The command field provides the control information for the transfer. The Unibus I/0 interface unit allows the Unibus device to act as master on the Emmy bus. The 18-bit Unibus address is mapped into the 24-bit Emmy address space through the address translation unit, where the command field is also generated. A mapping scheme is used which utilizes a page setup register file to associate dynamically one of fifty-four 2K halfword pages with a 1K fullword Emmy page. The microprogramed sequencer receives commands from the master unit on either bus system and provides all the sequence control for the specified operation. Data path is designed into two parts; one is the halfword part for most of the transfers, and the other, fullword part, is used mainly for transfer to/from the control store and other high-speed devices. The address translation facility provides mapping of pages in the Unibus address space other than the base pages (occupied by 4K core memory) and the upper pages which by convention are reserved for use as device registers. The entire address space of each bus system is available to the other system. 5 figures.

• Research Organization: Stanford Univ., CA (USA). Digital Systems Lab.
• OSTI ID: 7318689
• Report Number(s): SU-326-P.39-19
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990200* -- Mathematics & Computers
COMPUTERS
DESIGN
EQUIPMENT INTERFACES
PDP COMPUTERS
SIMULATION
SPECIFICATIONS