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U.S. Department of Energy
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SiO sub x precipitation: Defect density correlation with the n sup + substrate resistivity

Conference ·
OSTI ID:7249663

The thermal budget of a CMOS process, which employs n/n{sup +} epitaxial silicon, can constrain the SiO{sub x} precipitation necessary for bulk gettering sites. This makes the control of both the precipitation and its distribution difficult. Little or no precipitation will occur when heat treatments are inadequate or the n{sup +} substrate O{sub 2} concentration (O) is too low. Likewise, uncontrolled precipitation can lead to warpage, slip and the formation of surface stacking faults. Bulk precipitation is some CMOS processes using n/n{sup +} epitaxial silicon may not be feasible, because of the smaller thermal budgets. However; many CMOS processes using n/n{sup +} epitaxial silicon rely on some form of gettering. Extrinsic and intrinsic gettering techniques as well as pre-processed gettered wafers can be employed with CMOS processes to develop the necessary internal SiO{sub x} defects for effective gettering . An experimental strategy was designed to determine how the CMOS thermal budget interacts with the extrinsic gettering layers on n{sup +} substrates with different (O). Models for the defect densities and denuded zones developed from the strategy are reported for the polysilicon (Poly) and polysilicon/nitride (PN) extrinsic gettering layers. An unexpected correlation between the defect density and the n{sup +} substrate resistivity with (O) also is discussed. 10 refs., 1 fig., 3 tabs.

Research Organization:
Sandia National Labs., Albuquerque, NM (USA)
Sponsoring Organization:
DOE/DP
DOE Contract Number:
AC04-76DP00789
OSTI ID:
7249663
Report Number(s):
SAND-89-1930C; CONF-900562--1; ON: DE90005593
Country of Publication:
United States
Language:
English