Extrinsic gettering for VLSI/ULSI processes
Gettering techniques are employed to reduce metallic impurities that can be accumulated during device processing. The removal of these metallic impurities from active device regions improves device yield, oxide integrity, and other device parameters. Intrinsic (IG) and extrinsic (EG) gettering techiques are reported to be effective, but may not be as effective for small geometry processing because of possible problems regarding reproducibility and uniformity of oxygen precipitation phenomena. Object of this investigation was to develop an EG technique in which a uniform internal defect formation is formed for a n/n/sup +/ epitaxial structure. The use of medium and high oxygen content n/sup +/ substrates with and without poly/nitride EG layers for a 2.0..mu..m to 1.0 ..mu..m p-well CMOS process is reported.
- Research Organization:
- Sandia National Labs., Albuquerque, NM (USA); KMI, Inc., Albuquerque, NM (USA)
- DOE Contract Number:
- AC04-76DP00789
- OSTI ID:
- 6727415
- Report Number(s):
- SAND-86-1945C; CONF-870513-1; ON: DE87002696
- Country of Publication:
- United States
- Language:
- English
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