Multiple processor accelerator for logic simulation

Patent · Tue Oct 03 00:00:00 EDT 1989

OSTI ID:7222551

Catlin, G M

This patent describes a computer system coupled to a plurality of users for implementing an event driven algorithm of each of the users. It comprises: a master processor coupled to the users for providing overall control of the computer system and for executing the event driven algorithm of each of the users, wherein the master processor further includes a master memory; a unidirectional ring bus coupled to the master processor; a plurality of processor modules coupled to the unidirectional ring bus, wherein the unidirectional ring bus transfers data among the processor modules and the master processor.

• Assignee: Daisy Systems Corp., Mountain View, CA
• Patent Number(s): US 4872125
• Application Number: PPN: US 7142721A
• OSTI ID: 7222551
• Resource Relation: Patent File Date: 11 Jan 1988
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE
ARRAY PROCESSORS
DATA PROCESSING
ALGORITHMS
COMPUTER ARCHITECTURE
COMPUTERIZED SIMULATION
MEMORY DEVICES
MEMORY MANAGEMENT
MATHEMATICAL LOGIC
PROCESSING
SIMULATION
990200* - Mathematics & Computers