Performance of parallel linear algebra algorithms on an interleaved array processor

Thesis/Dissertation · Wed Jan 01 04:00:00 EST 1986

OSTI ID:6891624

Wolf, G

This thesis investigates the performance of numerical algorithms that take advantage of the unique properties of a new type of array processor. This processor, called an Interleaved Array Processor (IAP), is characterized by its ability to use multiple Programmable Functional Units (PFU's) with local data and instruction memories. Unlike conventional array processors, which can only execute simple arithmetic vector operations such as addition and multiplication, the IAP can execute complex vector operations defined by the user. These operations are specified by small programs that can contain conditional branching as well as arithmetic and data movement instructions in each processor. The author calls these programs High-Level Vector Operations (HLVO's). Ways to partition the algorithms and the data among the processing units in the system are presented so that in such a way that the computation time in every processing unit is increased, and at the same time the data movement on the system bus, is reduced. In this way the bus can be timeshared among several functional units, allowing several operations on different vector components to be executed simultaneously and overlapped with the transfer of operands and results.

• Research Organization: Rice Univ., Houston, TX (USA)
• OSTI ID: 6891624
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990210* -- Supercomputers-- (1987-1989)
990300 -- Information Handling
ALGORITHMS
ARRAY PROCESSORS
DATA PROCESSING
MATHEMATICAL LOGIC
PERFORMANCE
PROCESSING
PROGRAMMING
TASK SCHEDULING
VECTOR PROCESSING