Modified lightly doped drain MOSFET for very large scale integration
Reducing MOSFET dimensions while maintaining a constant-supply voltage leads to higher electric fields inside the active regions of VLSI transistors. Operation of micron and submicron MOSFETs in the presence of high-field effects has required design innovations so that a constant-supply voltage, acceptable punch-through voltage, and long-term reliability are possible as device scaling continues. Drain engineering is necessary to cope with the susceptibility of MOSFETs to hot-carrier-related degradation. Reducing the electric fields at the drain end of the channel is critical to device reliability because degradation is related to carrier heating as they traverse regions with field strength in excess of 100 kV/cm. Optimized lightly doped drain (LDD) structures that spread the high electric field at the drain ensure the reliable 5-V operation of micron-sized n-channel MOSFETs. Recent experimental evidence revealed that LDDFETs are less reliable than conventional transistors if the n/sup -/ region is too lightly doped. A JFET is merged into the n-MOS structure to reduce the high fields under the gate. Two-dimensional simulations and experimental results demonstrate for the first time the operation of this device and its potential for VLSI applications requiring maximum supply voltage.
- Research Organization:
- Stanford Univ., CA (USA)
- OSTI ID:
- 7198545
- Country of Publication:
- United States
- Language:
- English
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