A RAM based CMOS histogrammer integrated circuit

Conference · Mon Feb 01 04:00:00 EST 1988 · IEEE Trans. Nucl. Sci.; (United States)

OSTI ID:7183608

Slorach, F; Alsford, J R

A Histogramming integrated circuit has been designed with 256 24 bit cells, the pipelined RAM based architecture has been designed to give histogram capture rates of at least 8 Mhz. The chip is capable of histogramming an entire 512 X 512 image with an eight bit grey level in real time, and is fully cascadable for both increased historgram resolution or capacity. The RAM is accessable for random read/write operations through the 24 bit data and 8 bit address busses. Additional features include global thresholding, sequential read/clear and a simple self test on the RAM. The chip was designed using an integrated design system with a ramcell compiler and is being fabricated on a 2 micron CMOS technology.

• Research Organization: Rutherford Appleton Lab., Chilton, Oxon (GB)
• OSTI ID: 7183608
• Report Number(s): CONF-871006-
• Conference Information: Journal Name: IEEE Trans. Nucl. Sci.; (United States) Journal Volume: 35:1
• Country of Publication: United States
• Language: English

Related Subjects

42 ENGINEERING
420800 -- Engineering-- Electronic Circuits & Devices-- (-1989)
99 GENERAL AND MISCELLANEOUS
990220* -- Computers
Computerized Models
& Computer Programs-- (1987-1989)
COMPUTER CODES
DATA-FLOW PROCESSING
DESIGN
ELECTRONIC CIRCUITS
EXECUTIVE CODES
INTEGRATED CIRCUITS
MICROELECTRONIC CIRCUITS
PROGRAMMING