A synthesis algorithm for reconfigurable interconnection networks
The performance of a parallel algorithm depends in part on the interconnection topology of the target parallel system. An interconnection network is called reconfigurable if tis topology can be changed between different algorithm executions. Since communication patterns vary from one parallel algorithm to another, a reconfigurable network can effectively support algorithms with different communication requirements. In this paper, the authors describe how to generate a network topology that is optimized with respect to the communication patterns of a given task. The algorithm presented takes as input a task graph and generates as output a topology that closely matches the given input graph. The topologies generated by the authors' algorithm are analyzed with respect to optimum interconnection topologies for the best, worst, and average cases. Simulation results verify the average case performance prediction and confirm that, on the average, the optimum topologies are generated.
- Research Organization:
- General Robotics and Active Sensory Processing Group, Dept. of Computer and Information Science, Moore School of Electrical Engineering, Univ. of Pennsylvania, Philadelphia, PA (US)
- OSTI ID:
- 7169725
- Journal Information:
- IEEE Trans. Comput.; (United States), Journal Name: IEEE Trans. Comput.; (United States) Vol. 37:6; ISSN ITCOB
- Country of Publication:
- United States
- Language:
- English
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