Scalable coherent interface
Conference
·
OSTI ID:7164494
- Dolphin Server Technology A.S., Oslo (Norway)
- Stanford Linear Accelerator Center, Menlo Park, CA (USA)
- Apple Computer, Cupertino, CA (USA)
The Scalable Coherent Interface (IEEE P1596) is establishing an interface standard for very high performance multiprocessors, supporting a cache-coherent-memory model scalable to systems with up to 64K nodes. This Scalable Coherent Interface (SCI) will supply a peak bandwidth per node of 1 GigaByte/second. The SCI standard should facilitate assembly of processor, memory, I/O and bus bridge cards from multiple vendors into massively parallel systems with throughput far above what is possible today. The SCI standard encompasses two levels of interface, a physical level and a logical level. The physical level specifies electrical, mechanical and thermal characteristics of connectors and cards that meet the standard. The logical level describes the address space, data transfer protocols, cache coherence mechanisms, synchronization primitives and error recovery. In this paper we address logical level issues such as packet formats, packet transmission, transaction handshake, flow control, and cache coherence. 11 refs., 10 figs.
- Research Organization:
- Stanford Linear Accelerator Center, Menlo Park, CA (USA)
- Sponsoring Organization:
- DOE/ER
- DOE Contract Number:
- AC03-76SF00515
- OSTI ID:
- 7164494
- Report Number(s):
- SLAC-PUB-5184; CONF-9005132--1; ON: DE90008011
- Country of Publication:
- United States
- Language:
- English
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