Behavior analysis of CMOS D flip-flops

Journal Article · Sun Oct 01 00:00:00 EDT 1989 · IEEE Journal of Solid-State Circuits (Institute of Electrical and Electronics Engineers); (USA)

DOI:https://doi.org/10.1109/JSSC.1989.572637· OSTI ID:7140261

Chao, H J; Johnston, C A ^[1]

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1. Bellcore, Morristown, NJ (US)

In this paper, the authors analyze two {ital D} flip-flops (DFF's) generally considered to be the fastest (and most widely used), and compare their speed performance and their robustness against clock skew when a two-phase clocking scheme is applied. The effect of clock skew on their speed and proper logic operation is analyzed and verified with SPICE simulation.

• OSTI ID: 7140261
• Journal Information: IEEE Journal of Solid-State Circuits (Institute of Electrical and Electronics Engineers); (USA), Vol. 24:5; ISSN 0018-9200
• Country of Publication: United States
• Language: English

Related Subjects

42 ENGINEERING
99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE
FLIP-FLOP CIRCUITS
PERFORMANCE TESTING
MOS TRANSISTORS
COMPUTERIZED SIMULATION
S CODES
COMPUTER CODES
ELECTRONIC CIRCUITS
MULTIVIBRATORS
PULSE CIRCUITS
SEMICONDUCTOR DEVICES
SIMULATION
TESTING
TRANSISTORS
426000* - Engineering- Components
Electron Devices & Circuits- (1990-)
990200 - Mathematics & Computers