Superconducting Shuttle-Flux Shift Register for Race Logic and Its Applications
Journal Article
·
· IEEE Transactions on Circuits and Systems I: Regular Papers
- Lawrence Berkeley National Laboratory (LBNL), Berkeley, CA (United States). Applied Mathematics and Computational Research Division
Here this paper presents a superconducting, magnetically-coupled, shuttle-flux shift register (SF-SR) that stores single flux quantum (SFQ) pulses. This shift register has a DC bias operating margin of ±34% at 10 GHz, with a power dissipation of 3.6 μW and 38% fewer Josephson junctions (JJs) when scaled up to multiple stages compared to a data flip-flop (DFF) based shift register. The clock input is inductively coupled and is independent from the data input. We then present three applications for our SF-SR. In the first application, we add two non-destructive readout (NDRO) cells to construct a buffer that temporarily stores the temporal information of a series of race logic (RL) pulses. The second application is a pseudo-random number generator based on a linear function shift register (LFSR). The third application is N parallel SF-SRs that can act similar to a deserializer or instead can emulate a single SF-SR of N times higher clock frequency. These three applications motivate deep shift registers with many shifting intervals, which our SF-SR can implement with fewer JJs and lower power consumption compared to DFF-based shift registers.
- Research Organization:
- Lawrence Berkeley National Laboratory (LBNL), Berkeley, CA (United States)
- Sponsoring Organization:
- USDOE Office of Science (SC)
- Grant/Contract Number:
- AC02-05CH11231
- OSTI ID:
- 2326971
- Journal Information:
- IEEE Transactions on Circuits and Systems I: Regular Papers, Journal Name: IEEE Transactions on Circuits and Systems I: Regular Papers Journal Issue: 1 Vol. 70; ISSN 1549-8328
- Publisher:
- IEEECopyright Statement
- Country of Publication:
- United States
- Language:
- English
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