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U.S. Department of Energy
Office of Scientific and Technical Information

Layout system for printed circuit boards

Conference ·
OSTI ID:7126301

A computer-aided printed circuit board layout system which is now being used to produce a variety of PC board designs is described. The system is able to handle boards with arbitrary trimline geometries having up to about 100 IC's. It was designed to achieve 90-95 percent automatic connection rates on two layer boards, and has also been used to produce four layer boards.

Research Organization:
California Univ., Livermore (USA). Lawrence Livermore Lab.
DOE Contract Number:
W-7405-ENG-48
OSTI ID:
7126301
Report Number(s):
UCRL-78563(Rev.1); CONF-760934-4
Country of Publication:
United States
Language:
English

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