Circuit design for nuclear radiation test of CMOS multiplier chips
This paper describes the design of a microprocessor-based electronic circuit to be used in testing the effects of nuclear radiation on a CMOS 8 x 8 multiplier chip. Knowledge of such effects is important for military and space applications of integrated circuits. The multiplier chip undergoing testing is attached to a DUT (device under test) board which is enclosed in a metal container. The container is then lowered to the cobalt 60 radiation source located at the bottom of a 15-ft-deep pool. The gamma-ray radiation test setup is schematically shown. The in-source test board containing the multiplier chip is attached to an 8085-based, single-board microcomputer (SDK-85) by a 30-ft multiconductor cable. Doses of gamma-ray radiation from cobalt 60 are applied in steps at increasing quantities until the multiplier chip, which is tested between doses, begins to malfunction. An 8085 assembly language program is used for functional test of the multiplier. The leakage current and the propagation delay time are also measured between doses.
- Research Organization:
- Naval Research Lab. (US)
- OSTI ID:
- 7029563
- Journal Information:
- IEEE Circuits Devices; (United States), Journal Name: IEEE Circuits Devices; (United States) Vol. 2:5; ISSN ICDME
- Country of Publication:
- United States
- Language:
- English
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