Area estimation of VLSI circuits
Traditionally, the process of designing VLSI chips proceeded through specification all the way to chip layouts. At this point the resulting layout might have been too big to fit on a chip due to yield considerations which limit the size of the die. Under such circumstances the designer will have to redesign the circuit with modifications. This design-redesign sequence could be repeated several times, consuming time and money. This research aimed at reducing the design time by providing the designer with means of predicting the outcome of the various design steps prior to their execution. Two components contribute to the area of a chip: functional (or logic) and wiring. The first part of the thesis presents a probabilistic model for estimating the wiring area of standard-cell-type chip layouts. The model is verified through simulation. Validation with respect to real chip layouts indicated that the model estimates are accurate to within 10% of the actual area. Estimating the size of the logic in a circuit is investigated in the latter part of the thesis. It was assumed that the abstract functionality of a design is given in the form of a data flow graph, where nodes are operations and edges are values. The design cost is bounded by bounding the costs of the cheapest design and the fastest design.
- Research Organization:
- University of Southern California, Los Angeles (USA)
- OSTI ID:
- 7019945
- Country of Publication:
- United States
- Language:
- English
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