ISITE: Automatic circuit synthesis for double-metal CMOS VLSI circuits
Thesis/Dissertation
·
OSTI ID:5826764
Very large scale integrated (VLSI) circuit technology allows one to manufacture chips with several million devices. Designing such large circuits cannot be accomplished without design automation tools and computer-aided design tools. This thesis addresses the problem of automatic circuit synthesis for double-metal CMOS technology. Large circuits are partitioned into cells and represented as incidence matrices. The rows and columns of these matrices are folded to minimize the area. A symbolic layout is then generated for each matrix. This symbolic layout is then used to generate the physical mask layers necessary for fabrication in the metal-metal matrix methodology.
- Research Organization:
- Illinois Univ., Urbana, IL (USA)
- OSTI ID:
- 5826764
- Country of Publication:
- United States
- Language:
- English
Similar Records
Testable structures for CMOS VLSI circuits
Fast symbolic layout translocation for custom VLSI integrated circuits
Design automation for high-performance complementary metal-oxide-semiconductor VLSI circuits
Thesis/Dissertation
·
Wed Dec 31 23:00:00 EST 1986
·
OSTI ID:7245068
Fast symbolic layout translocation for custom VLSI integrated circuits
Thesis/Dissertation
·
Tue Dec 31 23:00:00 EST 1985
·
OSTI ID:5127872
Design automation for high-performance complementary metal-oxide-semiconductor VLSI circuits
Thesis/Dissertation
·
Sat Dec 31 23:00:00 EST 1988
·
OSTI ID:6472826