Asynchronous design for digital signal-processing architectures
A systematic procedure is described for designing fully asynchronous architectures from a structural description and an automated algorithm for synthesizing optimum asynchronous interconnection circuits with minimum hardward and maximum performance. Two computer-aided design tools, a synthesis program and an event-drive simulator designed especially for emulating hardward operations built of asynchronous component, have been developed to facilitate design automation for asynchronous systems. The author applied the design procedure to both programmable architectures and dedicated-hardware design and fabricated a chip set for implementing a high-sampling-rate adaptive filter using the asynchronous design techniques. He discusses the issues relevant to the design of an asynchronous programmable processor, such as pipelining, data-flow control, program flow control, feedback and initialization, I/O interface, and architectures. Simulation results for an asynchronous version of a commercial digital signal processor are given. He also addresses the system-level tradeoffs of using synchronous design vs. asynchronous design. From the test results of the chips, the quantifies the performance comparison of one technology point.
- Research Organization:
- California Univ., Berkeley, CA (USA)
- OSTI ID:
- 7019939
- Country of Publication:
- United States
- Language:
- English
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Related Subjects
426000 -- Engineering-- Components
Electron Devices & Circuits-- (1990-)
99 GENERAL AND MISCELLANEOUS
990200* -- Mathematics & Computers
ALGORITHMS
COMPUTER ARCHITECTURE
COMPUTER-AIDED DESIGN
DATA-FLOW PROCESSING
DIGITAL CIRCUITS
ELECTRONIC CIRCUITS
FABRICATION
MATHEMATICAL LOGIC
PROGRAMMING
SIGNAL CONDITIONING
SIMULATION
VECTOR PROCESSING