Coupled hardware and software architecture for programmable digital signal processors
Programmable signal-processor architectures using extensive concurrency are considered together with the programming of such architectures. A synchronous data flow (SDF) programming paradigm, a special case of data flow (either large grain or atomic), is proposed as an attractive way of partitioning signal-processing algorithms for concurrent execution on homogeneous parallel processors sharing memory. SDF programs are directed graphs where each arc represents a signal path and each node represents an operation. The number of samples consumed or produced each time a node is invoked is specified for each input or output path of each node. A SDF graph can be statically scheduled onto parallel processors, so the run-time overhead usually associated with data flow evaporates. It is shown how to identify errors in the construction of an SDF graph, such as sample-rate inconsistencies and directed loops with insufficient delay. It is proved that a broad class of algorithms will find a periodic schedule if one exists and give specific algorithms, for both single and parallel processors. In addition to homogeneous parallel processors, SDF can be used to program extensively pipelined single-processor architectures using an old but rarely used architectural approach. Multiple processes are interleaved through a single deeply pipelined processor.
- Research Organization:
- California Univ., Berkeley (USA)
- OSTI ID:
- 6963809
- Country of Publication:
- United States
- Language:
- English
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